Hi,

I am working on a project of filtering the network traffic using an FPGA spartan-6, and for this I must first find a VHDL IP stack and implement it on the FPGA board in order to send and receive IP packet.

So i'm writing to ask for a help to find an existing VHDL IP stack designed for FPGA spartan-6, because i can't find that on OpenCores.org projects.

Thanks.

me too facing same problem.... plz anybody help me...

(I know nothing of you or your project, so nothing here is intended to be condescending, I am just writing the way I would explain to a new hire)

Your terminology is misleading. You say a 'stack', but you want it in VHDL. So, I am going to assume you arent willing to do something in Microblaze (cause you could run a Linux stack there, or bare metal Xilinx app), also, I won't hold your choice of VHDL against you, but I only use Verilog. :)

You want to 'filter' packets, I can give you my recommendation, and you can email me to discuss details.

Take a look at the MAC IPs that are available (even on OpenCores), especially those supporting GMII Gigabit ethernet (avoid the 10/100 or trimode, they are bulky and not as easy to work with). Now, look at the timing diagrams for receiving and sending packets on the Rx[0-7] and Tx[0-7].

Look on google for GMII, scan the specs, lookup documentation for cores from Altera and Xilinx, you learn a lot by reading those. Get intimiately familiar with what those few signals mean and do together. I took an existing project and attached chipscope pro to the GMII wires, and stared at lots of traces.

Of course, I am assuming that you know all about packet structures, if you dont, you need to put in 20 hours using wireshark, and stepping through captured packets, and searching out all the information on the fields.

And then a good exercise is to write a one page Java/C program that takes a raw packet and builds another raw packet for a response, and verify that in wireshark. DO NOT attempt to put stuff in hardware that you cant define or code in software. (See last Line)

Assuming you have your little packet filter algorithm down to something really simple, (I mean only pointer increments, and if then logic), you are ready to try hardware.


Now, you want to 'filter packets', you can write a state machine that steps through each received byte (GigE is 125MHz I think, which is very forgiving for timing closure). Use registers to store values you might need, and then either buffer them through a BRAM, or shift them with SRL16s, and insert your 'filtered' packet back on to the MAC on the Tx side.

If you want to support more elaborate filtering, you can use a BRAM to store white list and black list IPs and netmasks, you will just have to delay your packets long enough to check all the entries.

There are no 'stacks' in hardware design, just nets and registers. Welcome to the bare metal world. The advantage is that we once wrote a simple VoIP media server that fit into 10% of a Virtex2 Pro/20. It was so fast that we were able to transmit response packets before we finished receiving requests sometimes. But it did one thing, and one thing only.

The disadvantage is that there is no place to hide bad engineering, wishful thinking, and prayer.

Garbage in Garbage out applies in hardware design as well.

TMB